1. Field of the Invention
This invention pertains generally to memory cells, and more particularly to nano-electro-mechanical memory cells.
2. Description of Related Art
Non-volatile memory, such as FLASH, is the fastest growing segment of the semiconductor memory market, due to burgeoning demand for highly functional mobile consumer electronics, including cellular phones, digital cameras, camcorders, personal digital assistants, MP3 players, and so forth. The traditional floating-gate FLASH memory cell as shown in FIG. 1, faces significant challenges in being scaled to gate lengths below 100 nm, or worse yet below 10 nm, in view of its thick gate-stack equivalent oxide thickness (EOT).
This scalability issue has been partially assuaged by employing a high-permittivity dielectric (e.g., SiNx or HfO2) charge-storage layer thus allowing a thinner tunnel dielectric to be employed, and/or a thin-body transistor structure such as the double-gate FinFET thus providing improved suppression of short-channel effects, particularly drain-induced barrier lowering. For this reason, FinFET SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) FLASH memory devices recently have been pursued by the industry, showing promise for scaling to gate lengths of less than 50 nm.
Floating-gate and SONOS-type memory cell designs require high program/erase voltages (e.g., greater than 10V) and are relatively slow to program (e.g., greater 10 μs write time), due to the requirement of a thick (greater than 2 nm) tunnel dielectric to ensure a long retention time, such as a ten year retention time. These characteristics pose a challenge for reducing power consumption and cost, which is particularly important for portable electronics applications. Thus, alternative memory cell designs which allow very high storage density with low voltage operation are desirable, to meet future data storage requirements.
In order to achieve very high storage density rivaling that of hard-disk drives, a memory technology should be stackable; that is, allow for multiple layers of storage cells to be fabricated over CMOS circuitry at reasonable cost. The non-volatile memory technology illustrated in FIG. 2 is an example of a stackable technology; however, it is not re-programmable as the memory structure is based on anti-fuse storage elements in each cell.
Stackable non-volatile memory technologies that are reprogrammable, such as resistive RAM technologies (e.g., magneto-resistive RAM (MRAM), organic RAM, and phase change memory), are being investigated for ultra-high-density non-volatile data storage applications. These have performance characteristics that are superior to FLASH memory technology, for example high endurance (e.g., up to 1015 write/erase cycles), sub-100 nS read and write speeds, and low operating voltage (e.g., less than 5 Volts).
Among the emerging memory technologies, the front-runners are MRAM and ferroelectric RAM (FeRAM). However, a significant drawback to these technologies is their reliance on non-standard materials which increase process complexity and hence cost. Furthermore, these technologies require a selection device (e.g., a diode or a transistor) within each cell to ensure reasonable sense margins and to prevent data disturbances. The fabrication of stackable selection devices with good performance and uniformity presents significant technological challenges.
Within the next few years MOSFET gate lengths and operating voltages are expected to be scaled down to below 10 nm and below 1 Volt operating levels, respectively. It will be recognized that FLASH memory transistors are more difficult to scale because of the thick gate-stack equivalent oxide thickness (EOT) required in order to meet charge storage (threshold voltage shift) and retention requirements. Although advanced transistor structures can be leveraged to improve gate-length scalability, high program/erase voltages are still required for fast operation. Thus, alternative integrated-circuit memory technologies, such as magnetic RAM (MRAM) and phase-change memory (PCM), have been heavily investigated in recent years. These alternative memory technologies require new materials, which increase process complexity and hence cost, while their scalability to sub-10 nm cell size is not assured. In view of this a need exists for a new non-volatile memory technology that is scalable (in size and operating voltage) in a similar manner as logic devices.
In addition, 3-D stackable memory technologies such as resistive RAM (RRAM) are being investigated for ultra-high density non-volatile data storage applications. As was the case with FeRAM described above, this technology also requires non-standard materials and the use of selection devices within each cell to ensure reasonable sense margins and to prevent data disturbances.
Development is proceeding directed at carbon nanotubes with state value set in response to adhesion between two nanotubes (e.g., NEMS-based memory). In principle, this NEMS-based technology can achieve high density due to the very small diameter of nanotubes; however, methods for precisely and economically growing/placing nanotubes in a regular array have yet to be developed. Furthermore, similar to other RRAM technologies, NRAM suffers from the leakage problem (from other cells along the same bit-line) during read operation and hence requires a selection device within each cell.
Accordingly, a need exists for an apparatus and method of 3-D stackable selection devices with sufficient performance, uniformity and suitability for mass fabrication. These needs and others are met within the present invention which utilizes conventional integrated-circuit materials to overcome the deficiencies of previously developed non-volatile memory technologies.